# -----------------------------------------------------------------------------
# Copyright (c) 2025, Southeast University (China)
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#  - Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
#  - Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#  - Neither the name of the copyright holders nor the names of its
#    contributors may be used to endorse or promote products derived from
#    this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jiajie Xu, Yanfang Zhang, Jiaqi Gao, Leyun Tian
# -----------------------------------------------------------------------------


set sh_message_limit 0
set sdc_save_source_file_information            true

# Timing variable
set svr_keep_unconnected_nets                   true
set timing_save_pin_arrival_and_slack           true
set timing_report_unconstrained_paths           true

set timing_enable_max_capacitance_set_case_analysis true
# CPRP
set timing_remove_clock_reconvergence_pessimism false
# set timing_crpr_threshold_ps                    5.0
#set timing_clock_reconvergence_pessimism        normal
#set timing_input_port_default_clock             false

# Wireload
#set auto_wire_load_selection false

# To prevent the gating signal propagating into the clock
#set timing_clock_gating_propagate_enable        true

# SI
if {$is_si_enabled} {
  set si_enable_analysis                    true
  set si_xtalk_double_switching_mode        clock_network
  set si_xtalk_analysis_effort_level        high
#  set si_xtalk_reselect_delta_delay         0.01
#  set si_xtalk_reselect_delta_delay_ratio   0.95
#  set si_xtalk_reselect_max_mode_slack      0
#  set si_xtalk_reselect_min_mode_slack      0
#  set si_xtalk_reselect_clock_network       true
  set si_analysis_logical_correlation_mode  false
  set si_xtalk_exit_on_max_iteration_count  3
}

set power_enable_analysis True
set rc_cache_min_max_rise_fall_ceff True
set sdf_enable_cond_start_end True

# set_app_var report_default_significant_digits 13